Worst-case execution time

Results: 108



#Item
81Electronics / Electronic engineering / WCET / Response time / Static timing analysis / Operating system / Analysis / Method / Embedded system / Real-time computing / Worst-case execution time / Technology

Evaluation of Methods for Dynamic Time Analysis for CC-Systems AB Yina Zhang Augusti 13, 2005

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Source URL: www.mrtc.mdh.se

Language: English - Date: 2005-08-21 14:31:51
82WCET / Compiler optimization / Local Interconnect Network / Response time / Electronics / Computing / Real-time computing / Worst-case execution time / Technology

Applying Static WCET Analysis to Automotive Communication Software Susanna Byhlin, Andreas Ermedahl, Jan Gustafsson and Bj¨orn Lisper Dept. of Computer Science and Electronics, M¨alardalen University Box 883, S[removed]

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Source URL: www.mrtc.mdh.se

Language: English - Date: 2005-08-20 14:36:55
83Computing / Electronics / Real-time computing / Worst-case execution time / Technology

Evaluation of Static Time Analysis for CC Systems Ola Eriksson [removed[removed]

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Source URL: www.mrtc.mdh.se

Language: English - Date: 2005-08-21 14:32:00
84Real-time computing / Worst-case execution time / Procedural programming languages / Model-driven engineering / Stack / C / Debugging / Software bug / Analysis / Computing / Software engineering / Computer programming

Towards Model-Driven Development of Hard Real-Time Systems Integrating ASCET and aiT/StackAnalyzer Christian Ferdinand1 , Reinhold Heckmann1 , Hans-J¨org Wolff2 , Christian Renz2 , Oleg Parshin3 , and Reinhard Wilhelm3

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Source URL: www.absint.com

Language: English - Date: 2011-01-26 09:33:00
85Compiler construction / Real-time computing / Worst-case execution time / Compiler optimizations / Compiler / Loop optimization / Code generation / Control flow graph / GNU Compiler Collection / Software / Programming language implementation / Computing

Design of a WCET-Aware C Compiler ∗ Heiko Falk Paul Lokuciejewski Henrik Theiling

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Source URL: www.absint.com

Language: English - Date: 2011-01-26 09:32:50
86Technology / Avionics / Safety / Software requirements / Pharmaceutical industry / Astrée / DO-178B / Worst-case execution time / Formal verification / Embedded systems / Software development / Computing

Abstract Interpretation Founded in 1998, AbsInt is a privately-held company located in Saarbrücken, Germany. AbsInt provides advanced development tools and tools for validation, verification, and certification of safety

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Source URL: www.absint.com

Language: English - Date: 2014-05-14 04:39:47
87Technology / Worst-case execution time / CPU cache / Parallel computing / Computer / Central processing unit / Pointer / Out-of-order execution / Real-time computing / Computing / Electronics

COMPUTING THE WORST CASE EXECUTION TIME OF AN AVIONICS PROGRAM BY ABSTRACT INTERPRETATION Jean Souyris* ([removed]), Erwan Le Pavec* ([removed]), Guillaume Himbert* (guillaume.himbert@airbus.

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Source URL: www.absint.com

Language: English - Date: 2011-01-26 09:33:00
88Computing / Programming language implementation / WCET / Benchmark / Usability / Compiler / Electronics / Technology / Real-time computing / Worst-case execution time

manuscript No. (will be inserted by the editor) Lili Tan The Worst Case Execution Time Tool Challenge 2006:

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Source URL: www.absint.com

Language: English - Date: 2011-01-26 09:32:50
89Technology / Real-time computing / Worst-case execution time / Central processing unit / CPU cache / DO-178B / Debugging / Cache / Pipeline / Computing / Embedded systems / Electronics

aiT Worst-Case Execution Time Analyzer Timing Validation for Real-Time Systems aiT WCET Analyzer computes tight bounds for the worst-case execution time of tasks in safety-critical systems. These bounds are safe, i.e. th

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Source URL: www.absint.com

Language: English - Date: 2014-11-14 06:34:31
90CPU cache / Latency / Cache / Worst-case execution time / Synchronous dynamic random-access memory / Parallel computing / Conventional PCI / Dynamic random-access memory / Computer hardware / Computer memory / Computing

Timing Anomalies in Multi-core Architectures due to the Interference on the Shared Resources Hardik Shah, Kai Huang and Alois Knoll Department of Informatics VI, Technical University Munich, 85748 Garching, Germany. {sha

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Source URL: www6.in.tum.de

Language: English - Date: 2013-12-19 04:43:37
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